Q: You've talked about the leakage current (Ileak)
for MOS capacitors used in the loop filter. 
For 130nm process, what is the approximate Ileak?
 
A: I already knew roughly the answer to "how much leakage"
to expect in a 130nm process but could not disclose any proprietary data. 

Fortunately, from Google results I discovered that
the SIA (Semiconductor Industry Association) 
roadmap reports that the thin gate oxide thickness
(material:silicon dioxide) is 22 Angstrom 
for 130nm technology and 16 Angstrom for 90nm.

At Vg = 1V, the gate leakage is about 0.01Amps/cm^2
for tox=22A and about 10Amps/cm^2 for tox=16A.
Note the approximate 1000X leakage difference 
between 90nm and 130nm technologies.

These results are for NMOS devices. PMOS leakage 
is probably about 2-5X smaller than NMOS leakage 
at high gate voltages. NMOS and PMOS gate leakage 
are similar at gate voltages below say 0.3V.

These quoted oxide thicknesses are "physical" values, 
not "electrical". Because of depletion in the gate 
poly and other effects, the "electrical" thickness 
is 5 or more Angstroms larger than the physical thickness.
So, in your spice models for 130nm mosfets, 
you'll see "tox" set at about 27-28A, not 22A.

Gate leakage is highly voltage dependent. For voltages
between about 0.6V to 1.2V, assume that the gate leakage
increases by roughly the 4th-power of the voltage. 
e.g. the gate leakage at 1.2V is about 15-20X higher 
than at 0.6V.

Gate leakage is not highly temperature dependent. 
From 25C to 100C, the leakage may increase by 
10% or less.

Finally, how does this leakage affect the PLL?

In 130nm, if the electrical oxide thickness is 27A,
then the gate capacitance per um^2 is about 12.7 fF.
That implies that it requires 7900 um^2 to build a
100pF cap. At a gate leakage of 0.01A/cm^2(=0.1nA/um2),
your gate leakage at Vctl=1V is 7900*0.1nA = 790nA. 
Fortunately, the leakage will be 15X smaller at Vctl=0.5V.

If the leakage is 790nA, your charge-pump current is
10uA and your reference period is 20nS, then the gate
leakage will create a static phase error of 1.6nS!
This static phase error will generate VCO jitter as
well. The solution is to use metal or thick gate
oxide (IO) caps.

In 90nm CMOS, the problem gets about 500-1000X worse,
and so you absolutely need metal or thick-gate oxide caps.

For reference:

Static Phase Error Equation:
----------------------------
Terr = Tref* (Ileak/Icp)

Capacitance Density Calculation:
---------------------------------
Cap(in Farad/m^2) = 3.9*8.854e-12/27e-10.